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Ordering number : ENN*6838
CMOS IC
LC86P7248
8-Bit Single-Chip Microcontroller with the One-Time Programmable PROM Built in
Preliminary Overview
The LC86P7248 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC867200 series. This microcontroller has the function and the pin description of the LC867200 series mask ROM version, and 48K-byte EPROM. QIP package are available for shipping as well as LC867200 series. It is suitable to set up first release, prototyping, developing and testing of set.
Features
(1) Option switching by PROM data The option function of the LC867200 series can be specified by the PROM data. LC86P7248 can be checked the functions of the trial pieces using the mass production board. (2) Internal one-time PROM capacity : 49408 bytes (3) Internal RAM capacity : 1152 bytes Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P7248.
Mask ROM version LC867248 LC867240 LC867232 LC867224 EPROM capacity 49152 bytes 40960 bytes 32768 bytes 24576 bytes RAM capacity 1152 bytes 1152 bytes 1152 bytes 1152 bytes
Programming service
We offers various services at nominal charges. These include ROM writing, ROM reading and package stamping and screening. Contact local our representative for further information.
Ver.1.02 72396
D2700 RM (IM) SK No.6838-1/20
LC86P7248 (4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 1s to 366s (6) Operating temperature : -30C to +70C (7) The pin compatible with the LC867200 series mask ROM devices (8) Applicable mask ROM version : LC867248/LC867240/LC867232/LC867224 (9) Factory shipment : QIP100E
Notice for use
LC86P7248 is provided for the first release and small shipping of the LC867200 series. At using, take notice of the followings. (1) A point of difference LC86P7248 and LC867200 series
Item Operation after reset releasing LC86P7248 The option is specified until 3ms after going to a `H' level to the reset terminal by degrees. The program is executed from 00H of the program counter. 4.5V to 6.0V LC867248/40/32/24 The program is executed from 00H of the program counter immediately after going to a `H' level to the reset terminal. 2.5V to 6.0V
Operating supply voltage range (VDD) Power dissipation
Refer to `electrical characteristics' on the semiconductor news.
LC86P7248 uses 256 bytes that is addressed on 0FF00H to FFFFH in the program memory as the option configuration data area. This option configuration can execute all options which LC867200 series have. * A kind of the option of the LC86P7248
A kind of option Input/output form of input/output ports Pins, Circuits Port 0 Contents of the option 1. N-channel open drain output 2. CMOS output *1 1. Pull-up MOS Tr. 2. No Pull-up MOS Tr. *2 1. Input : Programmable pull-up MOS Tr. Output : N-channel open drain 2. Input : Programmable pull-up MOS Tr. Output : CMOS 1. Input : No Programmable pull-up MOS Tr. Output : N-channel open drain 2. Input : Programmable pull-up MOS Tr. Output : CMOS 1. No Pull-up MOS Tr. 2. Pull-up MOS Tr.
Port 1
*1 Port 3
*1 Pull-up MOS Tr. of input port Ports 70, 71, 72, 73 *1
*1) Specified in a bit. *2) Specified in nibble unit.
Pull-up MOS Tr. is not provided in N-channel open drain output port.
No.6838-2/20
LC86P7248 (1) Option The option data is created by the option specified program "SU86K.EXE". program area by linkage loader "L86K.EXE". The created option data is linked to the
(2) ROM space LC86P7248 and LC867200 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH.
0FFFFH 0FF00H 0EFFFH 0DFFFH 0CFFFH 0BFFFH 0AFFFH 9FFFH 8FFFH 7FFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH 0FFFH 0000H
Option data area 256 bytes
Option data area
Option data area
Option data area
Program area 48K bytes LC867248
Program area 40K bytes LC867240
Program area 32K bytes LC867232
Program area 24K bytes LC867224
(3) Ordering information 1. When ordering the identical mask ROM and PROM devices simultaneously. Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask ROM and PROM versions. 2. When ordering a PROM device. Provide an EPROM containing the target memory contents together with an order form.
No.6838-3/20
LC86P7248
How to use
(1) Specification of option Programming data for PROM of the LC86P7248 is required. Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P7248. (2) How to program for the PROM The LC86P7248 can be programmed by PROM programmer with attachment ; W86EP7248Q * Recommended EPROM programmer
Productor Advantest Andou AVAL Minato electronics EPROM programmer R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL1890A
* "27512 (Vpp=12.5V) Intel high speed programming" mode available. jumper (DASEC) must be set to `OFF' at programming.
The address must be set to "0 to 0FFFFH" and a
(3) How to use the data security function "Data security" is the disabled function to read the data of the PROM. The following is the process in order to execute the data security. 1. Set `ON' the jumper of attachment. 2. Program again. Then PROM programmer displays the error. The error means normally activity of the data security. It is not a trouble of the PROM programmer or the LSI. Notes * Data security is not executed when the data of all address have `FFH' at the sequence 2 above. * The programming by a sequential operation "BLANK=>PROGRAM=>VERIFY" cannot be executed data security at the sequence 2 above. * Set to `OFF' the jumper after executing the data security.
Data security
Not data security
W86EP7248Q
No.6838-4/20
LC86P7248
Pin Assignment
V3/PL6 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 VSS2 VDD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 V2/PL5 V1/PL4 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30 P31 VSS3 VDD3 P32 P33 P34 P35 P00 P01 P02 P03 P04 P05 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
Notes * The QIP packages should be heat-soaked for 12 hours at 125C immediately prior to mounting (This baking is called pre-baking). * After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. Please solder within 24 hours.
Package Dimension (unit : mm)
3151
P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM0 P70/INT0 RES XT1/P74 XT2/P75 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN S0/PA0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1
SANYO : QIP-100E
No.6838-5/20
LC86P7248
System Block Diagram
Interrupt Control
IR
PLA
A15-A0 D7-D0 TA CE OE DASEC
Stand-by Control EPROM Control Clock Generator CF RC X'tal PC
EPROM (48KB)
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0
Port 8 ALU
Timer 1
Port 3
Real Time Service
ADC
PSW
RAM 128 bytes
INT0 to 3 Noise Rejection Filter
RAR
LCD Display Controller
RAM
SO0 to S7 (PA) S8 to S13 (PB) S16 to S23 (PC) S24 to S31 (PD) S32 to S39 (PE) S40 to S47 (PF) COM0 to -COM3(PL) Watchdog Timer Port 0 Stack Pointer
No.6838-6/20
LC86P7248
Pin Description
Pin name I/O VSS1, 2, 3 *1 VDD1, 2, 3 *1 PORT0 I/O P00 to P07 Function description Power pin (-) Power pin (+) * 8-bit input/output port Input/output in nibble units * Input for port 0 interrupt * Input for HOLD release Option * Pull-up resistor : Provided/Not provided (specified in nibble units) * Output form (P00 - P07) : CMOS/N-channel open drain (specified in a bit) * Output form : CMOS/N-channel open drain (specified in a bit) PROM mode
PORT1 I/O P10 to P17
PORT3 I/O P30 to P35 PORT7
* 8-bit input/output port Input/output can be specified in bit unit * Other pin functions P10 : SIO0 data output P11 : SIO0 data input/bus input/output P12 : SIO0 clock input/output P13 : SIO1 data output P14 : SIO1 data input/bus input/output P15 : SIO1 clock input/output P16 : Buzzer output P17 : Timer1 output (PWM output) * 6-bit input/output port * Input/output can be specified in bit unit
Data line D0 to D7
* 6-bit input port * Other pin functions I/O P70 P70 : INT0 input/HOLD release input/ N-ch Tr. output for watchdog timer P71 to P73 I P71 : INT1 input/HOLD release input P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input * Interrupt received form, vector address rising falling rising high low & level level falling INT0 enable enable disable enable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable I P74 , P75 P74 : XT1 terminal for crystal oscillation Port8 P80 to P87 I P75 : XT2 terminal for crystal oscillation * 8-bit input port * Other function AD input port (8 port pins)
* Output form : CMOS/N-channel open drain (specified in a bit) Pull-up resistor : Provided/Not provided (specified in a bit) (P70, P71, P72, P73) * P74 , P75 don't have the pull-up resistor option.
-
Power for programming PROM control signals DASEC (*2) OE (*3)
CE (*4)
vector
03H 0BH 13H 1BH
-
-
No.6838-7/20
LC86P7248
Pin name Port A (S0/PA0 to S7/PA7) Port B (S8/PB0 to S15/PB7) Port C (S16/PC0 to S23/PC7) I/O I/O Function description * Segment output terminal for LCD display * Can be used as a general input/output port * Segment output terminal for LCD display * Can be used as a general input/output port * Segment output terminal for LCD display * Can be used as a general input/output port Option PROM mode Address input A0 to A7 Address input A8 to A13 PROM control signal input * TA (*5) Address input * A14, A15 -
I/O
-
I/O
-
Port D (S24/PD0 to S31/PD7) Port E (S32/PE0 to S39/PE7) Port F (S40/PF0 to S47/PF7) Port L (COM0/PL0 to
COM3/PL3)
I/O
I/O
I/O
I/O
* Segment output terminal for LCD display * Can be used as a general input/output port * Segment output terminal for LCD display * Can be used as a general input/output port * Segment output terminal for LCD display * Can be used as a general input/output port * Common output terminal for LCD display * Can be used as a general input port * Bias power terminal for LCD drive * Can be used as a general input port Reset pin * Input pin for 32.768kHz crystal oscillation In case of non use, connect to VDD. * Other function A general input port P74 * Output pin for 32.768kHz crystal oscillation In case of non use, should be left unconnected * Other function A general input port P75 Input pin for ceramic resonator oscillation Output pin for ceramic resonator oscillation
-
-
-
-
-
-
-
V1/PL4 - V3/PL6
RES
I I I
-
-
XT1/ P74
XT2/P75
O
-
-
(I) CF1 CF2 I O
-
-
* All of port options can be specified in bit unit except the pull-up resistor of port 0. [Notes] * The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other. * The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other. *1 Connect like the following figure to reduce noise into a VDD terminals. *2 Memory select input for data security *3 Output enable input *4 Chip enable input *5 TA ! PROM control signal input
Power Supply
LSI VDD1
VDD2 VDD3 VSS1 VSS2 VSS3
No.6838-8/20
LC86P7248 1. Absolute Maximum Ratings at Ta=25C, VSS=VSS1=VSS2=VSS3=0V
Parameter Supply voltage LCD display voltage Input voltage Symbol Pins Conditions VDD1=VDD2= VDD3 VDD1=VDD2= VDD3 Ratings typ. unit V
VDD[V]
Input/output voltage High Peak level output output current current Total output current
VDDMAX VDD1, VDD2 VDD3 VLCD V1/PL6, V2/PL5 V3/PL4 VI *Ports 71, 72, 73 *Ports 74 , 75 *Port 8, Port L * RES VIO *Port 0, 1, 3 *Port 70 *Ports A,B,C,D,E,F IOPH(1) Ports 0, 1, 3 IOPH(2) Ports A,B,C,D,E,F IOAH(1) IOAH(2) IOAH(3) vIOAH(4) IOPL(1) IOPL(2) IOPL(3) IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) Pdmax Ports 0, 1, 32, 33, 34, 35 Ports 30, 31 Ports S0 to S25 Ports S26 to S47 Ports 0, 1, 3 Ports A,B,C,D,E,F Port 70 Ports 0, 1, 32, 33, 34, 35 Ports 30, 31 Ports S0 to S25 Ports S26 to S47 Port 70 QIP100E
min. -0.3 -0.3 -0.3
max. +7.0 VDD VDD+0.3
-0.3
VDD+0.3
*CMOS output *At each pins Total all pins Total all pins Total all pins Total all pins At each pins At each pins At each pins Total all pins Total all pins Total all pins Total all pins Total all pins Ta=-30 to +70C
-4 -4 -38 -4 -25 -25 20 20 15 50 20 39 33 10 515
mA
Low level output current
Peak output current Total output current
Maximum power dissipation Operating temperature range Storage temperature range
mW C
Topr
-30
+70
Tstg
-55
+125
Notes * The QIP packages should be heat-soaked for 12 hours at 125C immediately prior to mounting (This baking is called pre-baking). * After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6838-9/20
LC86P7248 2. Recommended Operating Range at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V
Parameter Operating supply voltage range Hold voltage Symbol VDD(1) VDD(2) VHD VDD1=VDD2= VDD3 Port 0 *Ports 1, 3 *Ports A,B,C,D,E,F,L *Ports 72, 73 *Port 70 Port input/interrupt *Port 71 * RES Port 70 Watchdog timer *Port 8 *Port 74 ,75 Port 0 *Ports 1, 3 *Ports A,B,C,D,E,F,L *Ports 72, 73 *Port 70 Port input/interrupt *Port 71 * RES Port 70 Watchdog timer *Port 8 *Port 74 ,75 Pins VDD1=VDD2= VDD3 Conditions 0.98s tCYC 400s 3.9s tCYC 400s RAMs and the registers hold voltage at HOLD mode. Output disable Output disable Ratings typ. unit V
VDD[V]
min. 4.5 2.5 2.0
max. 6.0 6.0 6.0
Input high voltage
VIH(1) VIH(2)
4.5 to 6.0 0.4VDD +0.9 4.5 to 6.0 0.75VDD
VDD VDD
VIH(3)
Output N-channel Tr. OFF
4.5 to 6.0 0.75VDD
VDD
VIH(4) VIH(5) Input low voltage VIL(1) VIL(2)
Output N-channel Tr. OFF Using as port Output disable Output disable
4.5 to 6.0 0.9VDD 4.5-6.0 0.75VDD 4.5 to 6.0 4.5 to 6.0 VSS VSS
VDD VDD 0.2VDD 0.25VDD
VIL(3)
Output N-channel Tr. OFF
4.5 to 6.0
VSS
0.25VDD
VIL(4) VIL(5) Operation cycle time Oscillation frequency range (Note 1) tCYC FmCF(1)
Output N-channel Tr. OFF Using as port
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
VSS VSS 0.98 6
0.8VDD -1.0 0.25VDD 400 s MHz
CF1, CF2
*6MHz (ceramic
resonator oscillation)
4.5 to 6.0
FmCF(2)
CF1, CF2
FmRC FsXtal
XT1, XT2
Oscillation stabilizing time period (Note 1)
tmsCF(1)
CF1, CF2
tmsCF(2)
CF1, CF2
tssXtal
XT1, XT2
*Refer to figure 1 *3MHz (ceramic resonator oscillation) *Refer to figure 1 RC oscillation *32.768kHz (crystal oscillation) *Refer to figure 2 *6MHz (ceramic resonator oscillation) *Refer to figure 3 *3MHz (ceramic resonator oscillation) *Refer to figure 3 *32.768kHz (crystal oscillation) *Refer to figure 3
4.5 to 6.0
3
4.5 to 6.0 4.5 to 6.0
0.4
0.8 32.768
3.0 kHz
4.5 to 6.0
ms
4.5 to 6.0
4.5 to 6.0
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6838-10/20
LC86P7248 3. Electrical Characteristics at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V
Parameter Input high current Symbol IIH(1) Pins *Port 1 *Port 0 without pull-up MOS Tr. Conditions *Output disable *Pull-up MOS Tr. OFF. VIN=VDD (including the offleak current of the output Tr.) VIN=VDD Ratings typ. unit A
VDD[V] 4.5 to 6.0
min.
max. 1
IIH(2)
IIH(3) IIH(4) IIH(5) IIH(6) Input low current IIL(1)
*Port 7 without pull-up MOS Tr. *Port 8 Port 3 Ports A,B,C,D,E,F,L
RES
4.5 to 6.0
1
VIN=VDD VIN=VDD VIN=VDD Using as port VIN=VDD *Output disable *Pull-up MOS Tr. OFF. VIN=VSS (including the offleak current of the output Tr.) VIN=VSS
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 -1
1 1 1 1
Ports 74 ,75 *Port 1 *Port 0 without pull-up MOS Tr.
IIL(2)
IIL(3) IIL(4) IIL(5) IIL(6) Output high voltage VOH(1) VOH(2)
*Port 7 without pull-up MOS Tr. *Port 8 Port 3 Ports A,B,C,D,E,F,L
RES
4.5 to 6.0
-1
VIN=VSS VIN=VSS VIN=VSS Using as port VIN=VSS IOH=-1.0mA IOH=-1.0mA
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
-1 -1 -1 -1 V
Ports 74 ,75 Ports 0,1 of CMOS output *Port 3 of CMOS output *Ports A,B,C,D,E,F of CMOS output Ports 0, 1 Port 70 Port 3 Ports A,B,C,D,E,F Of CMOS output
4.5 to 6.0 VDD-1 4.5 to 6.0 VDD-1
Output low voltage
VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7)
IOL=10mA IOL=1.6mA IOL=1mA IOL=10mA IOL=1.6mA IOL=8mA IOL=1.6mA
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
1.5 0.4 0.4 1.5 0.4 1.5 0.4
Continue.
No.6838-11/20
LC86P7248
Ratings typ.
Parameter LCD output regulation
Symbol VODLS
Pins S0 to S47
Conditions *Deference voltage to ideal value *VLCD, 2/3VLCD, 1/3VLCD
VDD[V] 4.5 to 6.0
min. 0
max. 0.2
unit V
VODLC
COM0 to COM3
4.5 to 6.0 *Deference voltage to ideal value *VLCD, 2/3VLCD, 1/2VLCD, 1/3VLCD Resistance at a ladder resistor *Resistance at a ladder resistor *1/2R mode 4.5 to 6.0 4.5 to 6.0
0
0.2
LCD ladder resistor
RLCD(1) RLCD(2)
60 30
k
Pull-up MOS Tr. resistor Hysteresis voltage Pin capacitance
Rpu
*Ports 0, 1, 3 *Ports A,B,C,D,E,F *Ports 70, 71, 72, 73 *Port 1 *Ports 70, 71, 72, 73 * RES All pins
VOH=0.9VDD
4.5 to 6.0
15
40
70
VHIS
Output disable
4.5 to 6.0
0.1VDD
V
CP
*f=1MHz *Unmeasurement terminals for the input are set to VSS level. *Ta=25C
4.5 to 6.0
10
pF
4. Serial Input/Output Characteristics at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V
Parameter Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Input clock Symbol tCKCY(1) tCKL(1) tCKH(1) tCKCY(2) tCKL(2) tCKH(2) tICK *SI0,SI1 *SB0,SB1 SCK0, SCK1 *Use pull-up resistor (1k) when open drain output. *Refer to figure 5. *Data set-up to SCK0, 1 *Data hold from SCK0, 1 *Refer to figure 5. *Use pull-up resistor (1k) when open drain output. *Data hold from SCK0, 1 *Refer to figure 5. 4.5 to 6.0 Pins SCK0, SCK1 Conditions Refer to figure 5. Ratings typ. unit tCYC
VDD[V] 4.5 to 6.0
min. 2 1 1 2
max.
Serial clock
Output clock
1/2 tCKCY 1/2 tCKCY 4.5 to 6.0 0.1 s
Serial input
Data set up time
Data hold time Output delay time (Serial clock is external clock) Output delay time (Serial clock is internal clock)
tCKI tCKO(1) *SO0, SO1 *SB0, SB1
4.5 to 6.0 4.5 to 6.0
0.1
7/12tCYC +0.2
Serial output
tCKO(2)
4.5 to 6.0
1/3tCYC +0.2
No.6838-12/20
LC86P7248 5. Pulse Input Conditions at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) Pins *INT0, INT1 *INT2/T0IN INT3/T0IN (The noise rejection clock is selected to 1/1.) INT3/T0IN (The noise rejection clock is selected to 1/16.) INT3/T0IN (The noise rejection clock is selected to 1/64.)
RES
Conditions *Interrupt acceptable *Timer0-countable *Interrupt acceptable *Timer0-countable
VDD[V] 4.5 to 6.0 4.5 to 6.0
min. 1 2
Ratings typ.
max.
unit tCYC
tPIH(3) tPIL(3)
*Interrupt acceptable *Timer0-countable
4.5 to 6.0
32
tPIH(4) tPIL(4)
*Interrupt acceptable *Timer0-countable
4.5 to 6.0
128
tPIL(5)
Reset acceptable
4.5 to 6.0
200
s
6. AD Converter Characteristics at Ta=-30C to + 70C, VSS=VSS1=VSS2=VSS3=0V
Parameter Resolution Absolute precision (Note 2) Conversion time Symbol NAD ETAD tCAD Pins Conditions Ratings typ. max. 8 1.5 65.28 (tCYC= 4.08s) 130.56 (tCYC= 4.08s) VDD 1 -1 V A
VDD[V] 4.5 to 6.0 4.5 to 6.0
min.
unit bit LSB s
Analog input voltage range Analog port input current
VAIN IAINH IAINL
AN0 - AN7
AD conversion time = 4.5 to 6.0 16 x tCYC (ADCR2=0) (Note 3) AD conversion time = 32 x tCYC (ADCR2=1) (Note 3) 4.5 to 6.0 VAIN=VDD VAIN=VSS 4.5 to 6.0 4.5 to 6.0
15.68 (tCYC= 0.98s) 31.36 (tCYC= 0.98s) VSS
(Note 2) Absolute precision excepts quantizing error (1/2 LSB). (Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital conversion value to the register.
No.6838-13/20
LC86P7248 7. Current Dissipation Characteristics at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V
Parameter Current dissipation during basic operation (Note 4) Symbol IDDOP(1) Pins VDD1= VDD2= VDD3 Conditions *FmCF=6MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *1/1 divided *FmCF=3MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *1/2 divided *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : RC oscillation *1/2 divided *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : crystal oscillation *Internal RC oscillation stops *1/2 divided Ratings typ. 15 unit mA
VDD[V] 4.5 to 6.0
min.
max. 30
IDDOP(2)
4.5 to 6.0
6
15
IDDOP(3)
4.5 to 6.0
4
13
IDDOP(4)
4.5 to 6.0
4
9
Continue.
No.6838-14/20
LC86P7248
Ratings typ. 6
Parameter
Symbol
Pins
Conditions *HALT mode *FmCF=6MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *1/1 divided *HALT mode *FmCF=3MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *1/2 divided *HALT mode FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : RC oscillation *1/2 divided *HALT mode FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : crystal oscillation *Internal RC oscillation stops *1/2 divided HOLD mode
Current dissipation IDDHALT(1) VDD1= in HALT mode VDD2= (Note 4) VDD3
VDD[V] 4.5 to 6.0
min.
max. 11
unit mA
IDDHALT(2)
4.5 to 6.0
2.2
9
IDDHALT(3)
4.5 to 6.0
500
1700
A
IDDHALT(4) IDDHALT(5)
4.5 to 6.0
25
100
Current dissipation IDDHOLD(1) VDD1= in HOLD mode VDD2= (Note 4) VDD3
4.5 to 6.0
0.05
30
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6838-15/20
LC86P7248 Table 1. Ceramic resonator oscillation guaranteed constant (main clock)
Oscillation type 6MHz ceramic resonator oscillation 3MHz ceramic resonator oscillation Maker Oscillator C1 C2
* Both C1 and C2 must use K rank (10%) and SL characteristics. Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type 32.768kHz crystal oscillation Maker Oscillator C3 C4 Rd
(Notes)
* Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. * If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
Rd CF C1 C2 C3 X'tal C4
Figure 1
Ceramic oscillation circuit
Figure 2
Crystal oscillation circuit
No.6838-16/20
LC86P7248
Power supply Reset time
VDD VDD limit 0V
RES
Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution mode OCR6=1
Instruction execution mode
< Reset time and oscillation stable time >
HOLD release signal
Valid
Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2
Operation mode
HOLD
Instruction execution mode
< HOLD release signal and oscillation stable time >
Figure 3
Oscillation stable time
No.6838-17/20
LC86P7248
VDD
RRES RES CRES
(Note) Fix the value of CRES, RRES that is sure to reset until 200s, after Power supply has been over inferior limit of supply voltage.
Figure 4
Reset circuit
0.5VDD
< AC timing point >
tCKCY tCKL SCK0 SCK1 1k tICK SI0 SI1 tCKO S00, S01 SB0, SB1 50pF tCKI tCKH
VDD
< Timing > Figure 5 Serial input / output test condition
< Test load >
tPIL
tPIH
Figure 6
Pulse input timing condition
No.6838-18/20
LC86P7248
Notice for use
* The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for Sanyo to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed. * It is not possible to perform a writing test on the blank PROM. 100% yield, therefore, cannot be guaranteed.
* Keeping the dry packing The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. * After opening the packing The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the substrate. Note that the QIP package should be heat-soaked for 12 hours at 125C immediately prior to mounting (This baking is called pre-baking). After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. Please solder within 24 hours.
a. Shipping with a blank PROM (Programming the data by yourself)
b. Shipping with a programmed PROM (Programming the data by Sanyo)
QIP
QIP
Writing data for program/Verifying
Baking before mounting 125C, 12 hours Baking
Recommended process of screening Heat-soak 1505C, 24 +1 Hr -0
Mounting Reading ascertain of program VDD=50.5V
Baking before mounting 125C, 12 hours Baking
Mounting
No.6838-19/20
LC86P7248 memo :
PS No.6838-20/20

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